The present invention relates to integrated-circuit memory arrays, including erasable programmable read-only-memory (EPROM or flash EPROM) arrays. In particular, the invention relates to sensing of currents during reading of such memories to determine whether or not a particular cell is programmed with a "1" or a "0".
An example of prior-art sensing circuitry is described in "A 29s 8 Mb EPROM with Dual Reference-Column ATD Sensing", Sweha et al., ISSCC 1991 (p. 264-265). A pseudodifferential sense amplifier using an equalization technique is discussed in "A 36ns 1 Mbit CMOS EPROM With New Data Sensing Technique", Nakai et al., 1990 Symposium on VLSI Circuits (p. 95-96).
U.S. Pat. Nos. 5,056,063; 5,126,974 and 5,206,552 disclose methods of improving the speed of current-mirror-type sense amplifiers including, in one of those example patents, use of differential amplifiers with positive feedback.
An EPROM cell typically comprises a floating-gate field-effect transistor. The floating-gate conductor of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a predetermined voltage is applied to the control gate. The nonconductive state is read by a sense amplifier as a "zero" bit. The floating-gate conductor of a non-programmed cell is neutrally charged (or slightly positively or negatively charged) such that the source-drain path under the non-programmed floating gate is conductive when the predetermined voltage is applied to the control gate. The conductive state is read by a sense amplifier as a "one" bit.
An EPROM array may contain millions of floating-gate memory cells arranged in rows and columns. The sources of each cell in a column are connected to a source-column line and the source-column line for a selected cell may be connected to reference potential or ground during reading of the selected cell by a sense amplifier. The drains of each cell in a column are connected to a separate bitline (drain-column line) and the drain-column line for a selected cell is connected to the input of the sense amplifier during reading of the selected cell. The control gates of each cell in a row are connected to a wordline, and the wordline for a selected cell is connected to the predetermined select voltage during reading of the selected cell.
During the read operation, the current through the selected cell is compared with a reference current to determine whether or not the selected cell is programmed with a "0" or a "1". The reference current is derived from reference circuitry, which may include one or more floating-gate cells identical to the cell being read or may include a column of such reference cells. The reference circuitry is connected to input of a first current-sensing amplifier. The output of the first current-sensing amplifier is connected to one side of a differential amplifier. The differential amplifier compares the voltage output of the first current-sensing amplifier with the voltage output of a second sensing amplifier connected to the selected memory cell being read. If the reference-circuitry comprises a memory cell that is essentially the same as the memory cell being read, it is generally necessary to unbalance the current-sensing amplifiers in order to arrive at a reference current between the current of selected cells programmed with a "0" and the current of selected cell programmed with a "1". In such prior-art sense amplifiers, in addition to the current-sensing amplifiers being unbalanced, but the loads connected to those current-sensing amplifiers are also unbalanced because the capacitance associated with the reference-circuitry differs from the capacitance associated with the memory cell being read. The difference in capacitance is generally either related to different bitline lengths and/or to the associated interconnect geometries.
Problems associated with such prior-art sensing methods include slow sensing speed and noise susceptibility. The slow sensing speed results primarily from the capacitance of the bitlines. There is a need for sense amplifier circuitry that increases sensing speed and decreases noise susceptibility.